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ICS9LPRS462 idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 low power clock for ati rs/rd600 series chipsets for amd cpus datasheet 1 description output features ati rd/rs600 series systems using amd cpus ? integrated series resistors on differential outputs greyhound compatible cpu outputs 2 - 0.7v low power differential cpu pairs 8 - 0.7v low power differential src pairs 4 - 0.7v low power differential atig pairs 1 - 66 mhz hypertransport clock 2 - 48mhz usb clocks 3 - 14.318mhz reference clocks features/benefits: key specifications cpu outputs cycle-to-cycle jitter <150ps src outputs cycle-to-cycle jitter < 125ps atig outputs cycle-to-cycle jitter < 125ps +/- 100ppm frequency accuracy on all outputs if ref is tuned to +/-100ppm 3 - programmable clock request pins for src and atig clocks atigclks are programmable for frequency spread spectrum for emi reduction outputs may be disabled via smbus external crystal load capacitors for maximum frequency accuracy pin configuration vdd gnd 5 8 usb_48 outputs 14,23,26,36 15,22,27,37 srcclk outputs 33 32 atigclk differential outputs 42 41 analog, pll 46 45 cpuclk8 differential outputs 52 50 httclk output 2 1 ref outputs pin number description fs2 fs1 fs0 cpu mhz htt mhz src mhz atig mhz usb mhz 000hi-zhi-z 100.00 100.00 48.00 0 0 1 x / 2 x / 3 100.00 100.00 48.00 0 1 0 230.00 76.67 100.00 100.00 48.00 0 1 1 240.00 80.00 100.00 100.00 48.00 1 0 0 100.00 66.66 100.00 100.00 48.00 1 0 1 133.33 66.66 100.00 100.00 48.00 1 1 0 166.67 66.66 100.00 100.00 48.00 1 1 1 200.00 66.66 100.00 100.00 48.00 funtionality power groups gndref 1 64 fs0/ref0 vddref 2 63 fs1/ref1 x1 3 62 fs2/ref2 x2 4 61 **pd vdd48 5 60 vddhtt 48mhz_0 6 59 httclk0 48mhz_1 7 58 gndhtt gnd48 8 57 *clkreqa# smbclk 9 56 cpukg0t_lpr smbdat 10 55 cpukg0c_lpr reset_in# 11 54 vddcpu src7t_lpr 12 53 gndcpu src7c_lpr 13 52 cpukg1t_lpr vddsrc 14 51 cpukg1c_lpr gndsrc 15 50 vdda src6t_lpr 16 49 gnda src6c_lpr 17 48 nc src5t_lpr 18 47 src0t_lpr src5c_lpr 19 46 src0c_lpr src4t_lpr 20 45 gndsrc src4c_lpr 21 44 vddsrc gndsrc 22 43 src1t_lpr vddsrc 23 42 src1c_lpr src3t_lpr 24 41 atig0t_lpr src3c_lpr 25 40 atig0c_lpr src2t_lpr 26 39 vddatig src2c_lpr 27 38 gndatig vddsrc 28 37 atig1t_lpr gndsrc 29 36 atig1c_lpr atig3t_lpr 30 35 atig2t_lpr atig3c_lpr 31 34 atig2c_lpr *clkreqb#32 33*clkreqc# 64-tssop * internal pull-up resistor ** internal pull-down resistor 9lprs462
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 2 pin description pin # pin name type description 1 gndref gnd ground pin for the ref outputs. 2 vddref pwr ref, xtal power supply, nominal 3.3v 3 x1 in crystal input, nominally 14.318mhz 4 x2 out crystal output, nominally 14.318mhz 5 vdd48 pwr power pin for the 48mhz outputs and core. 3.3v 6 48mhz_0 out 48mhz clock output. 7 48mhz_1 out 48mhz clock output. 8 gnd48 gnd ground pin for the 48mhz outputs 9 smbclk in clock pin of smbus circuitry, 5v tolerant. 10 smbdat i/o data pin for smbus circuitry, 5v tolerant. 11 reset_in# in real time falling edge triggered input, when asserted, the part initiates a power up reset with the smbus being reset to it's power up values, and all pll derived clo cks stopped for the duration of power up stabilization. ref outputs continue to run. 12 src7t_lpr out true clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 13 src7c_lpr out complement clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 14 vddsrc pwr supply for src, 3.3v nominal 15 gndsrc gnd ground pin for the src outputs 16 src6t_lpr out true clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 17 src6c_lpr out complement clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 18 src5t_lpr out true clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 19 src5c_lpr out complement clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 20 src4t_lpr out true clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 21 src4c_lpr out complement clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 22 gndsrc gnd ground pin for the src outputs 23 vddsrc pwr supply for src, 3.3v nominal 24 src3t_lpr out true clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 25 src3c_lpr out complement clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 26 src2t_lpr out true clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 27 src2c_lpr out complement clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 28 vddsrc pwr supply for src, 3.3v nominal 29 gndsrc gnd ground pin for the src outputs 30 atig3t_lpr out true clock of low-power differential push-pull pci-express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 31 atig3c_lpr out complementary clock of low-power differential push-pull pci-express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 32 *clkreqb# in programmable clock request pin for src/atig/sb_src outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = tri-state
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 3 pin description (continued) pin # pin name type description 33 *clkreqc# in programmable clock request pin for src/atig/sb_src outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = tri-state 34 atig2c_lpr out complementary clock of low-power differential push-pull pci-express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 35 atig2t_lpr out true clock of low-power differential push-pull pci-express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 36 atig1c_lpr out complementary clock of low-power differential push-pull pci-express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 37 atig1t_lpr out true clock of low-power differential push-pull pci-express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 38 gndatig gnd ground pin for the atig outputs 39 vddatig pwr power supply for atig core, nominal 3.3v 40 atig0c_lpr out complementary clock of low-power differential push-pull pci-express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 41 atig0t_lpr out true clock of low-power differential push-pull pci-express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 42 src1c_lpr out complement clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 43 src1t_lpr out true clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 44 vddsrc pwr supply for src, 3.3v nominal 45 gndsrc gnd ground pin for the src outputs 46 src0c_lpr out complement clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 47 src0t_lpr out true clock of low power differential src clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 48 nc nc no connect 49 gnda gnd ground for the analog core 50 vdda pwr 3.3v power for the analog core 51 cpukg1c_lpr out complementary signal of low-power differential push-pull amd k8 "greyhound" clock with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 52 cpukg1t_lpr out true signal of low-power differential push-pull amd k8 "greyhound" clock with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 53 gndcpu gnd ground pin for the cpu outputs 54 vddcpu pwr supply for cpu, 3.3v nominal 55 cpukg0c_lpr out complementary signal of low-power differential push-pull amd k8 "greyhound" clock with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 56 cpukg0t_lpr out true signal of low-power differential push-pull amd k8 "greyhound" clock with integrated 33 ohm series resistor. (no 50ohm shunt resistor to gnd needed) 57 *clkreqa# in programmable clock request pin for src/atig/sb_src outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = tri-state 58 gndhtt pwr ground pin for the htt outputs 59 httclk0 out 3.3v single ended 66mhz hyper transport clock 60 vddhtt pwr supply for htt clocks, nominal 3.3v. 61 **pd in enter /exit power down. 1 = power down, 0 = normal operation. 62 fs2/ref2 i/o frequency select latch input pin/ 3.3v 14.318mhz reference clock 63 fs1/ref1 i/o frequency select latch input pin/ 3.3v 14.318mhz reference clock 64 fs0/ref0 i/o frequency select latch input pin/ 3.3v 14.318mhz reference clock
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 4 general description the ICS9LPRS462 is a main clock synthesizer chip that provides all clocks required for ati rd/rs600-based systems. an smbus interface allows full control of the device. funtional block diagram control logic xtal osc. fixed pll 48mhz(1:0) ref(2:0) srcclk(7:0) x1 x2 pll cpu div pd smbdat smbclk fs(2:0) clkreqb# at i g div atigclk(3:0) cpuclk(1:0) clkreqc# i r e f src div htt div httclk0 reset_in# clkreqa#
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 5 absolute max parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd_a - v dd + 0.5v v 1 3.3v logic input supply voltage vdd_in - gnd - 0.5 v dd + 0.5v v 1 storage temperature ts - -65 150 c 1 ambient operating temp tambient - 070c 1 case temperature tcase - 115 c 1 input esd protection hbm esd prot - 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. electrical characteristics - input/supply/common output parameters parameter symbol conditions* min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 9lprs462, all outputs driven 200 ma 1 9lprs464, all outputs driven 180 ma 1 powerdown current i dd3.3pd all diff pairs low/low 21 ma 1 input frequency f i v dd = 3.3 v 14.31818 mhz 2 pin inductance l p in 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization t stab from vdd power-up or de- assertion of pd to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd cpu output enable after pd de-assertion 300 us 1 tfall_pd pd fall time of 5 ns 1 trise_pd pd rise time of 5 ns 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4ma1 smbclk/smbdat clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 smbclk/smbdat clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. input low current input capacitance i dd3.3op operating current 2 input frequency should be measured at the ref pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs.
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 6 ac electrical characteristics - low-power dif outputs: cpukg and htt parameter symbol conditions min typ max units notes crossing point variation ? v cross single-ended measurement 140 mv 1,2,5 frequency f spread specturm on 198.8 200 mhz 1,3 long term accuracy ppm spread specturm off -300 +300 ppm 1,11 rising edge slew rate s rise differential measurement 0.5 10 v/ns 1,4 falling edge slew rate s fall differential measurement 0.5 10 v/ns 1,4 slew rate variation t slvar single-ended measurement 20 % 1 cpu, dif htt jitter - cycle to c y cle cpuj c2c differential measurement 150 ps 1,6 accumulated jitter t jacc see notes 1 ns 1,7 peak to peak differential voltage v d(pk-pk) differential measurement 400 2400 mv 1,8 differential voltage v d differential measurement 200 1200 mv 1,9 duty cycle d cyc differential measurement 45 55 % 1 amplitude variation ? v d change in v d dc cycle to cycle -75 75 mv 1,10 cpu skew cpu skew10 differential measurement 100 ps 1 guaranteed by design and characterization, not 100% tested in production. minimum frequency is a result of 0.5% down spread spectrum 6 max difference of t cycle between any two adjacent cycles. 7 accumulated tjc.over a 10 s time period, measured with jit2 tie at 50ps interval. 8 vd(pk-pk) is the overall magnitude of the differential signal. 11 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 9 vd(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0v vd. vd(max) is the largest amplitude allowed. 10 the difference in magnitude of two adjacent vd_dc measurements. vd_dc is the stable post overshoot and ring-back part of the signal. single-ended measurement at crossing point. value is maximum ? minimum over all time. dc value of common mode is not important due to the blocking cap. differential measurement through the range of 100 mv, differential signal must remain monotonic and within slew rate spec when crossing through this region. 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#.
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 7 ac electrical characteristics - low-power dif outputs: src and atig parameter symbol conditions min typ max units notes rising edge slew rate t slr differential measurement 0.5 2 v/ns 1,2 falling edge slew rate t flr differential measurement 0.5 2 v/ns 1,2 slew rate variation t slvar single-ended measurement 20 % 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 src, atig, jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 src[5:0] skew src skew differential measurement 250 ps 1 sb_src[1:0] skew src skew differential measurement 100 ps 1 atig[3:0] skew src skew differential measurement 100 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# fa lling) 6 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of electrical characteristics - usb - 48mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t period 48.00mhz output nominal 20.8229 20.8344 ns 2 clock low time t low measure from < 0.6v 9.3750 11.4580 ns 2 clock high time t high measure from > 2.0v 9.3750 11.4580 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r_usb v ol = 0.4 v, v oh = 2.4 v 0.5 1.5 ns 1 fall time t f_usb v oh = 2.4 v, v ol = 0.4 v 0.5 1.5 ns 1 duty cycle d t1 v t = 1.5 v 45 55 %1 group skew t skew v t = 1.5 v 250 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 130 ps 1,2 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs = 33 ? (unless otherwise specified) 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 ics recommended and/or chipset vendor layout g uidelines must be followed to meet this specification output low current i ol output high current i oh
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 8 electrical characteristics - ref-14.318mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 0 100 ppm 1,2 clock period t period 14.318mhz output nominal 69.8270 69.84 69.8550 ns 2 clock low time t low measure from < 0.6v 30.9290 37.9130 ns 2 clock high time t high measure from > 2.0v 30.9290 37.9130 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 11.5ns1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 11.5ns1 skew t sk1 v t = 1.5 v 100 ps 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 300 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs = 33 ? (unless otherwise specified) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 9 table1: cpu and htt frequency selection table bit4 bit3 bit2 bit1 bit0 cpu ss_en cpu fs3 cpu fs2 cpu fs1 cpu fs0 0 0 0 0 0 hi-z hi-z none 0 0 0 0 1 x / 2 x / 3 none 0 0 0 1 0 230.00 76.67 none 15% 0 0 0 1 1 240.00 80.00 none 20% 0 0 1 0 0 100.00 66.67 none 0 0 1 0 1 133.33 66.67 none 0 0 1 1 0 166.67 66.67 none 0 0 1 1 1 200.00 66.67 none 0 1 0 0 0 250.00 83.33 none 25% 0 1 0 0 1 260.00 86.67 none 30% 0 1 0 1 0 270.00 90.00 none 35% 0 1 0 1 1 280.00 93.33 none 40% 0 1 1 0 0 102.00 68.00 none 0 1 1 0 1 136.00 68.00 none 0 1 1 1 0 170.00 68.00 none 0 1 1 1 1 204.00 68.00 none 1 0 0 0 0 210.00 70.00 -0.5% 5% 1 0 0 0 1 220.00 73.33 -0.5% 10% 1 0 0 1 0 230.00 76.67 -0.5% 15% 1 0 0 1 1 240.00 80.00 -0.5% 20% 1 0 1 0 0 100.00 66.67 -0.5% 1 0 1 0 1 133.33 66.67 -0.5% 1 0 1 1 0 166.67 66.67 -0.5% 1 0 1 1 1 200.00 66.67 -0.5% 1 1 0 0 0 250.00 83.33 -0.5% 25% 1 1 0 0 1 260.00 86.67 -0.5% 30% 1 1 0 1 0 270.00 90.00 -0.5% 35% 1 1 0 1 1 280.00 93.33 -0.5% 40% 1 1 1 0 0 102.00 68.00 -0.5% 1 1 1 0 1 136.00 68.00 -0.5% 1 1 1 1 0 170.00 68.00 -0.5% 1 1 1 1 1 204.00 68.00 -0.5% 0% 2% 2% 0% byte 0 cpuclk (2:0) (mhz) spread % overclock % htt (mhz)
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 10 table2: src frequency selection table bit3 bit2 bit1 bit0 src ss_en src fs3 src fs2 src fs1 src fs0 0 0 0 0 0 100.00 0 0% 0 0 0 0 1 101.00 0 1% 0 0 0 1 0 102.00 0 2% 0 0 0 1 1 103.00 0 3% 0 0 1 0 0 104.00 0 4% 0 0 1 0 1 105.00 0 5% 0 0 1 1 0 106.00 0 6% 0 0 1 1 1 107.00 0 7% 0 1 0 0 0 100.00 0 0% 0 1 0 0 1 101.00 0 1% 0 1 0 1 0 102.00 0 2% 0 1 0 1 1 103.00 0 3% 0 1 1 0 0 104.00 0 4% 0 1 1 0 1 105.00 0 5% 0 1 1 1 0 106.00 0 6% 0 1 1 1 1 107.00 0 7% 1 0 0 0 0 100.00 -0.25% 0% 1 0 0 0 1 101.00 -0.25% 1% 1 0 0 1 0 102.00 -0.25% 2% 1 0 0 1 1 103.00 -0.25% 3% 1 0 1 0 0 104.00 -0.25% 4% 1 0 1 0 1 105.00 -0.25% 5% 1 0 1 1 0 106.00 -0.25% 6% 1 0 1 1 1 107.00 -0.25% 7% 1 1 0 0 0 100.00 -0.5% 0% 1 1 0 0 1 101.00 -0.5% 1% 1 1 0 1 0 102.00 -0.5% 2% 1 1 0 1 1 103.00 -0.5% 3% 1 1 1 0 0 104.00 -0.5% 4% 1 1 1 0 1 105.00 -0.5% 5% 1 1 1 1 0 106.00 -0.5% 6% 1 1 1 1 1 107.00 -0.5% 7% byte 0 bit 5 spread % src overclock % src(7:0) (mhz) b y te 5
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 11 table3: atig frequency selection table bit4 bit3 bit1 bit0 atig ss_en atig fs3 atig fs2 atig fs1 atig fs0 0 0 0 0 0 100.00 0 0% 0 0 0 0 1 105.00 0 5% 0 0 0 1 0 110.00 0 10% 0 0 0 1 1 115.00 0 15% 0 0 1 0 0 120.00 0 20% 0 0 1 0 1 125.00 0 25% 0 0 1 1 0 130.00 0 30% 0 0 1 1 1 135.00 0 35% 0 1 0 0 0 100.00 0 0% 0 1 0 0 1 105.00 0 5% 0 1 0 1 0 110.00 0 10% 0 1 0 1 1 115.00 0 15% 0 1 1 0 0 120.00 0 20% 0 1 1 0 1 125.00 0 25% 0 1 1 1 0 130.00 0 30% 0 1 1 1 1 135.00 0 35% 1 0 0 0 0 100.00 -0.25% 0% 1 0 0 0 1 105.00 -0.25% 5% 1 0 0 1 0 110.00 -0.25% 10% 1 0 0 1 1 115.00 -0.25% 15% 1 0 1 0 0 120.00 -0.25% 20% 1 0 1 0 1 125.00 -0.25% 25% 1 0 1 1 0 130.00 -0.25% 30% 1 0 1 1 1 135.00 -0.25% 35% 1 1 0 0 0 100.00 -0.5% 0% 1 1 0 0 1 105.00 -0.5% 5% 1 1 0 1 0 110.00 -0.5% 10% 1 1 0 1 1 115.00 -0.5% 15% 1 1 1 0 0 120.00 -0.5% 20% 1 1 1 0 1 125.00 -0.5% 25% 1 1 1 1 0 130.00 -0.5% 30% 1 1 1 1 1 135.00 -0.5% 35% byte 0 bit 6 atig(2:0) (mhz) spread % atig overclock % byte 9
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 12 table 4: cpu divider ratios b19b(7:4) bit 00 01 10 11 msb 00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 15 0111 30 1011 60 1111 120 lsb address div address address div address div table 5: htt divider ratios b20b(3:0) bit 00 01 10 11 msb 00 0000 4 0100 8 1000 16 1100 32 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 15 0111 30 1011 60 1111 120 lsb address div address address div address div table 6: atig divider ratios b19b(3:0) bit 00 01 10 11 msb 00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 7 0111 14 1011 28 1111 56 lsb address div address address div address div divider (1:0) divider (3:2) divider (3:2) divider (1:0) divider (3:2) divider (1:0) cpu clock common recommendations for differential routing dimension or value unit figure 0.5 max inch 1 l1 length, route as coupled 93 ohm trace. l2 length, route as coupled 93 ohm trace. contact amd inch 1 l2 l2 l1 l1 3900pf +/-10% figure 1 cpu clock routing. low power output buffer w/integrated series resistor amd "greyhound" cpu input 3900pf +/-10% 93 ? +/-10% diff 93 ? +/-10% diff 169 ? +/-10%
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 13 src reference clock common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50 ohm trace. 0.5 max inch 2 l2 length, route as non-coupled 50 ohm trace. n/a inch 2 l3 length, route as non-coupled 50 ohm trace. n/a inch 2 rs 33 ohm 2 rt 49.9 ohm 2 down device differential routing dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 2 l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 2 differential routing to pci express connector dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch 3 l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 3 figure 2 down device routing. pci ex board down device ref_clk input l1 l4 l1? l4? figure 2 figure 3 pci express connector routing. low power output buffer w/integrated series resistor pci ex add in board ref_clk input l1 l4 l1? l4? figure 3 low power output buffer w/integrated series resistor
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 14 general smbus serial interface information for the ICS9LPRS462 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 15 smbus table: spread spectrum enable and cpu frequency select register byte 0 pin # name control function type 0 1 pwd bit 7 - fs source latched input or smbus frequency select rw latched inputs smbus 0 bit 6 - atig ss_en atig spread spectrum enable rw disable enable 0 bit 5 - src ss_en src spread spectrum enable rw disable enable 0 bit 4 - cpu ss_en cpu spread spectrum enable rw disable enable 0 bit 3 - cpu fs3 cpu freq select bit 3 rw 0 bit 2 - cpu fs2 cpu freq select bit 2 rw latch bit 1 - cpu fs1 cpu freq select bit 1 rw latch bit 0 - cpu fs0 cpu freq select bit 0 rw latch note: each spread spectrum enable bit is independent from the other. bit(6:4) must all set to "1" in order to enable spread for cpu, src and atig clocks. smbus table: output control register byte 1 pin # name control function type 0 1 pwd bit 7 7 48mhz_1 48mhz_1 output enable rw disable enable 1 bit 6 6 48mhz_0 48mhz_0 output enable rw disable enable 1 bit 5 54 ref2 ref2 output enable rw disable enable 1 bit 4 55 ref1 ref1 output enable rw disable enable 1 bit 3 56 ref0 ref0 output enable rw disable enable 1 bit 2 51 httclk0 httclk0 output enable rw disable enable 1 bit 1 44,43 cpuclk1 cpuclk1 output enable rw disable enable 1 bit 0 48,47 cpuclk0 cpuclk0 output enable rw disable enable 1 smbus table: atigclk and clkreqb# output control register byte 2 pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 31,30 atigclk1 atigclk1 output enable rw disable enable 1 bit 4 35,34 atigclk0 atigclk0 output enable rw disable enable 1 bit 3 20,21 reqbsrc2 clkreqb# controls src2 rw does not control controls 0 bit 2 0 bit 1 24,25 reqbsrc1 clkreqb# controls src1 rw does not control controls 0 bit 0 0 smbus table: srcclk output control register byte 3 pin # name control function type 0 1 pwd bit 7 12,13 srcclk5 rw disable enable 1 bit 6 16,17 srcclk4 rw disable enable 1 bit 5 18,19 srcclk3 rw disable enable 1 bit 4 20,21 srcclk2 rw disable enable 1 bit 3 reserved - - - 1 bit 2 24,25 srcclk1 rw disable enable 1 bit 1 reserved - - - 1 bit 0 39,38 srcclk0 rw disable enable 1 see table 1: cpu frequency selection table master output control. enables or disables output, regardless of clkreq# inputs. reserved reserved reserved reserved
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 16 smbus table: clkreqb# and clkreqc# output control register byte 4 pin # name control function type 0 1 pwd bit 7 12,13 reqasrc5 clkreqa# controls src5 rw does not control controls 0 bit 6 16,17 reqasrc4 clkreqa# controls src4 rw does not control controls 0 bit 5 18,19 reqasrc3 clkreqa# controls src3 rw does not control controls 0 bit 4 0 bit 3 0 bit 2 31,30 reqcatig1 clkreqc# controls atig1 rw does not control controls 0 bit 1 35,34 reqcatig0 clkreqc# controls atig0 rw does not control controls 0 bit 0 39,38 reqcsrc0 clkreqc# controls src0 rw does not control controls 0 smbus table: cpu stop control and src frequency select register byte 5 pin # name control function type 0 1 pwd bit 7 io_vout2 io output voltage select (most significant bit) rw 1 bit 6 io_vout1 io output voltage select rw 0 bit 5 io_vout0 io output voltage select (least significant bit) rw 1 bit 4 0 bit 3 - src fs3 src freq select bit 3 rw 0 bit 2 - src fs2 src freq select bit 2 rw 0 bit 1 - src fs1 src freq select bit 1 rw 0 bit 0 - src fs0 src freq select bit 0 rw 0 smbus table: device id register byte 6 pin # name control function type 0 1 pwd bit 7 - device id7 (msb) r - - 0 bit 6 - device id6 r - - 1 bit 5 -device id5 r - -1 bit 4 -device id4 r - -0 bit 3 -device id3 r - -0 bit 2 -device id2 r - -1 bit 1 -device id1 r - -0 bit 0 - device id0 (lsb) r - - 0 smbus table: revision and vendor id register byte 7 pin # name control function type 0 1 pwd bit 7 -rid3 r--0 bit 6 -rid2 r--0 bit 5 -rid1 r--0 bit 4 -rid0 r--0 bit 3 -vid3 r--0 bit 2 -vid2 r--0 bit 1 -vid1 r--0 bit 0 -vid0 r--1 vendor id see table 2: src frequency selection table device id revision id reserved see table 8: v_io selection (default is 0.8v) reserved reserved
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 17 smbus table: byte count register byte 8 pin # name control function type 0 1 pwd bit 7 - bc7 rw 0 bit 6 - bc6 rw 0 bit 5 - bc5 rw 0 bit 4 - bc4 rw 0 bit 3 - bc3 rw 1 bit 2 - bc2 rw 0 bit 1 - bc1 rw 0 bit 0 - bc0 rw 1 smbus table: ref2, 48mhz output strength control and atig frequency select register byte 9 pin # name control function type 0 1 pwd bit 7 54 ref2str ref2 strength control rw 1x 2x 1 bit 6 7 48mhz_1str 48mhz_1 strength control rw 1x 2x 1 bit 5 6 48mhz_0str 48mhz_0 strength control rw 1x 2x 1 bit 4 0 bit 3 - atig fs3 atig freq select bit 3 rw 0 bit 2 - atig fs2 atig freq select bit 2 rw 0 bit 1 - atig fs1 atig freq select bit 1 rw 0 bit 0 - atig fs0 atig freq select bit 0 rw 0 smbus table: plls m/n programming enable and ref1, ref0 output strength control register byte 10 pin # name control function type 0 1 pwd bit 7 - m/n_en plls m/n programming enable rw disable enable 0 bit 6 55 ref1str ref1 strength control rw 1x 2x 1 bit 5 56 ref0str ref0 strength control rw 1x 2x 1 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: cpu pll vco frequency control register byte 11 pin # name control function type 0 1 pwd bit 7 - n div8 n divider prog bit 8 rw x bit 6 - n div 9 n divider prog bit 9 rw x bit 5 - m div5 rw x bit 4 - m div4 rw x bit 3 - m div3 rw x bit 2 - m div2 rw x bit 1 - m div1 rw x bit 0 - m div0 rw x smbus table: cpu pll vco frequency control register byte 12 pin # name control function type 0 1 pwd bit 7 - n div7 rw x bit 6 - n div6 rw x bit 5 - n div5 rw x bit 4 - n div4 rw x bit 3 - n div3 rw x bit 2 - n div2 rw x bit 1 - n div1 rw x bit 0 - n div0 rw x the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] m divider programming bits reserved reserved reserved reserved reserved reserved byte count programming b(7:0) writing to this register will congiure how many bytes will be read back, default is 9 bytes. see table 3: atig frequency selection table n divider programming b(7:0) the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2]
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 18 smbus table: cpu pll spread spectrum control register byte 13 pin # name control function type 0 1 pwd bit 7 - ssp7 rw x bit 6 - ssp6 rw x bit 5 - ssp5 rw x bit 4 - ssp4 rw x bit 3 - ssp3 rw x bit 2 - ssp2 rw x bit 1 - ssp1 rw x bit 0 - ssp0 rw x smbus table: cpu pll spread spectrum control register byte 14 pin # name control function type 0 1 pwd bit 7 0 bit 6 - ssp14 rw x bit 5 - ssp13 rw x bit 4 - ssp12 rw x bit 3 - ssp11 rw x bit 2 - ssp10 rw x bit 1 - ssp9 rw x bit 0 - ssp8 rw x smbus table: atig pll vco frequency control register byte 15 pin # name control function type 0 1 pwd bit 7 - n div8 n divider prog bit 8 rw x bit 6 - n div9 n divider prog bit 9 rw x bit 5 - m div5 rw x bit 4 - m div4 rw x bit 3 - m div3 rw x bit 2 - m div2 rw x bit 1 - m div1 rw x bit 0 - m div0 rw x smbus table: atig pll vco frequency control register byte 16 pin # name control function type 0 1 pwd bit 7 - n div7 rw x bit 6 - n div6 rw x bit 5 - n div5 rw x bit 4 - n div4 rw x bit 3 - n div3 rw x bit 2 - n div2 rw x bit 1 - n div1 rw x bit 0 - n div0 rw x smbus table: atig pll spread spectrum control register byte 17 pin # name control function type 0 1 pwd bit 7 - ssp7 rw x bit 6 - ssp6 rw x bit 5 - ssp5 rw x bit 4 - ssp4 rw x bit 3 - ssp3 rw x bit 2 - ssp2 rw x bit 1 - ssp1 rw x bit 0 - ssp0 rw x the decimal representation of m and n divier in byte 17 and 18 will configure the vco frequency. default at power up = byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] spread spectrum programming b(7:0) these spread spectrum bits in byte 19 and 20 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. these spread spectrum bits in byte 13 and 14 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. reserved m divider programming bits n divider programming b(7:0) spread spectrum programming b(7:0) spread spectrum programming b(14:8) these spread spectrum bits in byte 13 and 14 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. the decimal representation of m and n divier in byte 17 and 18 will configure the vco frequency. default at power up = byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2]
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 19 smbus table: atig pll spread spectrum control register byte 18 pin # name control function type 0 1 pwd bit 7 0 bit 6 - ssp14 rw x bit 5 - ssp13 rw x bit 4 - ssp12 rw x bit 3 - ssp11 rw x bit 2 - ssp10 rw x bit 1 - ssp9 rw x bit 0 - ssp8 rw x smbus table: cpu and atig divider ratio programming bits select register byte 19 pin # name control function type 0 1 pwd bit 7 -cpu_div3 rw x bit 6 -cpu_div2 rw x bit 5 -cpu_div1 rw x bit 4 -cpu_div0 rw x bit 3 - atig_div3 rw x bit 2 - atig_div2 rw x bit 1 - atig_div1 rw x bit 0 - atig_div0 rw x smbus table: htt divider ratio programming bits select register byte 20 pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 -htt_div3 rw x bit 2 -htt_div2 rw x bit 1 -htt_div1 rw x bit 0 -htt_div0 rw x htt_divider ratio programming bits see table 6: htt divider ratios reserved see table 4: cpu divider ratios atig_divider ratio programming bits reserved reserved reserved spread spectrum programming b(14:8) these spread spectrum bits in byte 19 and 20 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. cpu_divider ratio programming bits reserved see table 5: atig divider ratios
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 20 reset_in# - assertion (transition from '1' to '0') the pin is a schmitt trigger input with debouncing. after it is triggered, ref clocks will wait for two clock cycle to asserting reset_in pin stops all the outputs including cpu, src, atig, pci and usb with the ref[2:0] running. be power down and re-power up, and smbus will be reloaded. it will take no more than 2.5ms for the clocks to come out with correct frequencies and no glitches. ** deassertion of reset_in# (transition from '0' to '1') has no effect on the clocks. ensure the reset_in is asserted. then, it will take 3us for the clocks to stop without glitches. the clock chip will 2.5ms max 3 us max 2 clock cycles reset_in# ref [2:0] *clks
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 21 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ICS9LPRS462 serve as dual signal functions to the device. during initial power- up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus idt tm /ics tm low power clock for ati rs/rd600 series chipsets for amd cpus 1378a?04/07/08 22 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information ics 9lprs462 y glft example: designation for tape and reel packaging lead free, rohs compliant package type g = tssop revision designator (will not correlate with datasheet revision) device type ics xxxx y g lf t min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa--0.10--.004 variations min max min max 64 16.90 17.10 .665 .673 10-0039 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153
ICS9LPRS462 low power clock for ati rs/rd600 series chipsets for amd cpus 23 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # a 4/7/2008 1. updated idd current. 2. added down device routing diagram and pci express connector routing diagram. 3. going to release. 4. updated rs on ref & usb to 33ohm. 5. corrected ref ppm to +/- 100ppm. 5,7-8,13 this product is protected by united states patent no. 7,342,420 and other patents.

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